1. Field of the Invention
The present invention generally relates to a static random access memory (SRAM), and more particularly to a system and method for resolving request collision in a single-port SRAM.
2. Description of the Prior Art
Static random access memory (SRAM) is a type of semiconductor memory that is faster than dynamic random access memory (DRAM), which needs to be periodically refreshed. Accordingly, the SRAM is usually used as video memory in the driver of a panel display such as a liquid crystal display (LCD). The SRAM can be categorized as a single-port SRAM or a multi-port SRAM. The former has only one read/write port, while the latter has two or more read/write ports that can be accessed by various requesters at the same time. As the multi-port SRAM needs larger chip area and consumes more power than the single-port SRAM, the single-port SRAM is preferably used in portable or handheld electronic devices, such as mobile phones.
However, the high-capacity and low-power single-port SRAM suffers a speed penalty when two (or more) requests collide, or, in other words, the requests occur within the same clock cycle. FIG. 1A shows an exemplary timing diagram illustrating the request collision in a conventional single-port SRAM. In the figure, a host sends external requests EXT_REQUEST to write data (that is, Data 1, Data 2, Data 3 and Data 4 in the figure) in sequence to the single-port SRAM during respective cycles (that is, cycle 1, cycle 2, cycle 3 and cycle 4). Unfortunately, an internal request INT_RD also demands data during the same cycle 1. In other words, the internal request collides with the external request about the Data 1. In order to resolve this problem, the sequencer of the SRAM provides adjusted timing as shown in FIG. 1B, in which the signal RAM_CLK is derived from the external request EXT_REQUEST, and the signal RAM_LE is derived from the internal request INT_RD. After the Data 1 has been written to the SRAM in cycle 1, the next cycle (that is, cycle 2) is reserved for use of the internal request. While the external request about the Data 2 is postponed until the following cycle (that is, cycle 3), all of the other external requests about the Data 3 and the Data 4 are also, respectively, postponed by one cycle.
Although the request collision can be solved by delaying all of the following requests for one cycle as discussed above, the conventional single-port SRAM disadvantageously suffers from a speed penalty (i.e., one-cycle postponement whenever request collision occurs). For that reason, a need has arisen to propose a novel single-port SRAM architecture and method with improved speed performance.